1. Technical Field
This invention disclosed broadly, relates to memory technology and more particularly, relates to improved static random access memory arrays.
2. Background Art
The segmented precharge architecture is an extension of the segmented word line architecture. This scheme reduces power dissipation by reducing the number of active columns (bit Lines). The vast majority of SRAMs equal to or larger than 64K use the segmented word line architecture.
Existing static RAMs are organized into storage cells which are driven by word lines and which are sensed by bit lines. In order to sense a memory cell, the bit lines have to be previously charged to a predetermined state so that once the cell is read out, it can charge the bit lines so that they can be read by the sense amplifier. In the prior art, each time a word line is driven, the bit lines have their storage charges reset prior to the word line actually reading out the states of the storage cells. The time necessary to reset the bit lines is called the bit line reset time or bit line precharge time.
Static RAMS are typically organized so that the word lines are organized in sections, for example, eight bytes. Each time a section is interrogated in the prior art, all eight word lines are driven and all of the bit lines in that section are also enabled. The precharging of the word lines uses power and takes bit line precharge time.
What is needed is an extension of the static page/column access mode across the full address space of a memory so as to increase access speed and reduce power dissipation. It is desirable that the extended segmented precharge architecture can be applied to a SRAM of any size or organization.